Semiconductor devices are typically manufactured on semiconductor wafers or other types of workpieces using sophisticated equipment and processes that enable reliable, high-quality manufacturing. The individual dies (e.g., devices) generally include integrated circuits and a plurality of bond-pads coupled to the integrated circuits. The bond-pads provide external contacts through which supply voltage, electrical signals, and other input/output parameters are transmitted to/from the integrated circuits. The bond-pads are usually very small, and they are typically arranged in dense arrays having a fine pitch between bond-pads. The wafers and dies can also be quite delicate. As a result, the dies are packaged to protect the dies and to connect the bond-pads to arrays of larger terminals that can be soldered to printed circuit boards.
Chip scale packages (CSPs) are semiconductor components that have outlines, or “footprints,” approximately the same size as the dies in the packages. CSPs typically include dense arrays of bond-pads and solder bumps on the bond-pads that permit the packages to be flip-chip mounted to substrates (e.g., module substrates or other circuit boards). Bumped dies are another type of semiconductor component that include dense arrays of solder bumps.
One challenge of manufacturing semiconductor components is cost effectively packaging the dies. The sizes of computers, cell phones, hand-held devices, and other electronic products are continually decreasing, but at the same time the performance of electronic products is increasing. The sizes of the dies accordingly decrease while the number of components in the dies significantly increases to meet the demands of the market. As a result, the number and density of input/output terminals on the dies increase. This can significantly increase the cost of manufacturing semiconductor components.
Several existing processes package high-performance semiconductor dies in six-sided CSPs that completely encapsulate the dies while the dies are arranged in the format of a wafer (i.e., wafer-level packaging). One existing wafer-level packaging process for CSPs includes cutting deep trenches on only the active side of the wafer between the dies and depositing a polymeric material on the active side to fill the trenches and cover the dies. The wafer is then thinned from the backside until the trenches are exposed such that each die is completely separated from adjacent dies by the polymeric material in the trenches. Another layer of the polymeric material is applied to the backside of the dies, and the assembly is then cut along the polymeric material in the trenches to separate the packaged dies from each other. This process accordingly forms six-sided packages that completely encapsulate the dies.
One challenge of fabricating such six-sided packages is that it is difficult to cut deep channels into the wafer (e.g., channels deeper than approximately 250 microns). As a result, the wafer must be thinned to a thickness less than the depth of trenches to expose the polymeric material in the channels before the backside of the dies is coated with the additional layer of the polymeric material. In many cases the wafer is thinned to less than 250 microns to isolate the dies between the polymeric material in the trenches. This can be problematic because such thin dies are subject to warping or bending. More specifically, because the polymeric material and the dies have significantly different thermal expansion coefficients, thermal cycling can cause extensive warping and even breakage of the very thin dies. Therefore, it would be desirable to package semiconductor dies using wafer-level packaging techniques that provide more robust packages.